Products

ZipAccel Compression and Decompression IP

Sandgate compression IP is delivered through CAST Inc. and consists of two independent hardware cores:

  • ZipAccel-C — Deflate compression (RFC1950/1951/1952)
  • ZipAccel-D — Inflate / decompression (RFC1950/1951/1952)

These are standalone streaming engines designed to offload CPUs and scale to very high throughput implementations.

Architecture Overview

Compression (ZipAccel-C)

ZipAccel-C implements the full deflate pipeline in hardware:

  1. Search Engine (LZ77)
    Detects repeated patterns and produces a stream of literals and length-distance pairs (LLDs).
    Two built-in architectures:
    • Systolic array (deterministic, high throughput, shallow history)
    • Hash-based (flexible, deeper history, higher compression efficiency)
  2. Huffman Encoder
    Encodes LLDs using:
    • Static Huffman
    • Dynamic Huffman
    • Stored (pass-through) blocks

The encoder automatically selects the optimal block type per data region based on compression efficiency.

Decompression (ZipAccel-D)

ZipAccel-D performs the inverse operation in a pipelined architecture:

  1. Header parsing and validation (RFC1950/1952)
  2. Block decoding (static, dynamic, or stored)
  3. Huffman decode → LLD stream
  4. History reconstruction using a circular buffer
  5. Output formatting and validation

Each input file is processed independently, with full error detection and reporting.

Streaming Model

Both cores operate on streaming data interfaces:

  • Input and output are file-oriented streams
  • File boundaries are explicitly defined by control signals (ip_first / ip_last)
  • Multiple files can be processed sequentially or interleaved (QoS support in compression)

The cores do not require a processor and can operate continuously in hardware pipelines.

Configurability

ZipAccel-C is highly configurable to match application requirements:

  • History size (up to 32KB)
  • Search depth and parallelism
  • Deflate block size
  • Static vs dynamic Huffman usage
  • Stored block thresholds
  • Multi-engine stacking for throughput scaling
  • Bus widths up to 1024 bits

Users can tune tradeoffs between:

  • Compression ratio
  • Latency
  • Area
  • Throughput

Scalability

Performance scales in two dimensions:

  1. Within a core
    • Multiple search engines feeding a single Huffman encoder
  2. Across cores
    • Multiple compression/decompression blocks operating in parallel

This enables:

  • 100 Gbps compression throughput in FPGA implementations

  • Linear scaling for ASIC designs

ECC and Reliability

Both cores support optional ECC on internal RAM structures:

  • Correctable errors are handled transparently
  • Uncorrectable errors result in:
    • Controlled fallback (compression), or
    • File-level error indication (op_error / op_memory_error)

ECC behavior is memory-specific and configurable. Internal mechanisms ensure that transient or single-cycle ECC events do not corrupt output silently.

Integration

Interfaces include:

  • Native streaming interface
  • AXI4-Stream wrappers
  • AXI4-Lite control/status (decompression)

Features:

  • Flow-controlled streaming (ready/valid handshake)
  • File-level error reporting
  • Optional QoS and file interleaving (compression)
  • Multi-core scheduling (decompression)

C Model and Design Exploration

ZipAccel-C is accompanied by a cycle-approximate C model:

  • Validates compression behavior
  • Evaluates compression ratio vs configuration
  • Enables application-specific tuning before RTL integration

This allows users to tailor the hardware to real data sets.

Modular IP Options

The Huffman encoder is available as a standalone IP block for users who wish to:

  • Integrate a custom LZ77 or alternative frontend
  • Build hybrid or domain-specific compression architectures

Documentation and Support

Comprehensive user manuals are provided, including:

  • Theory of operation
  • Interface specifications
  • Configuration guidance
  • Performance data
  • Integration examples

Support is provided through Sandgate and licensing partner CAST Inc..